1. Field of the Invention
The invention relates to a process of providing low k inter-layer dielectric deposition films in combination with photolithography using Si-containing resists to avoid the poisoning effect traditionally imparted when using photolithography on conventional low k materials.
2. Background Art
Integrated circuits are made up of a plurality of active and passive devices that include transistors, capacitors and resistors, and these devices are initially separated or isolated from one another and later connected together in order to form functional circuits through interconnect structures. The quality of these interconnect structures significantly affects the performance and reliability of the circuits, and interconnects are increasingly determining the limits of performance as well as the density of ultra large scale integrated circuits (ULSI).
In conventional interconnect structures one or more metal layers are utilized, and each metal layer is generally made from tungsten or aluminum alloys. In these interconnect structures, interlevel and intralevel dielectrics (ILDs), typically silicon dioxide (SiO2) is used to electrically isolate the active elements and different interconnect signal paths from each other. Further, in these interconnect structures, electrical connections between different interconnect levels are generally made through vias or holes formed in the ILD layers. These vias are typically filled with a metal, such as tungsten.
Lately, a great interest has been shown to replace SiO2 with low-dielectric-constant (low-k) materials as the ILD in these interconnect structures. These low-k materials function as insulators in integrated circuit (IC) interconnect structures because they reduce the interconnect capacitance. As such, these low-k materials tend to increase signal propagation speed while also reducing cross-talk noise and power dissipation in the interconnect structure.
Nevertheless, the use of low-k materials as ILD in the interconnect structure still requires the use of processes that occasion technical difficulties. For example, photolithography on conventional low k materials always present challenges due to resists poisoning effects or other integration-related issues.
A chemically amplified resist for electron beam lithography is disclosed in U.S. Pat. No. 6,171,755 B1. The process for preparing a chemically amplified resist is one in which a substrate, which can be precoated with a bottom resist, is coated with a chemically amplified resist containing
a polymer with dissolution-inhibiting groups that can be cleaved with acid catalysis,
a photoreactive compound, which upon electron irradiation releases a sulfonic acid with a pKa value≦2.5 (photo acid generator),
an electron-beam-sensitive sensitizer enhancing the exposure sensitivity of the resist, the sensitizer having the structure 
in which R1=OH or OR, R2=COOR where R=C1 to C5 alkyl; and
a solvent, dried, irradiated with an electron beam, and subjected to temperature treatment (PEB) and wet development followed by silylation and dry development of bottom resist when present.
A method of preventing photoresist poisoning from dielectric antireflecting coating in semiconductor fabrication is disclosed in U.S. Pat. No. 6,103,456. The process entails:                providing a dielectric insulation layer on a surface of a semiconductor substrate having a first conductive layer disposed in a selective region thereon such that the insulation layer overlies the region of the first conductive layer;        providing a silicon oxynitride layer on the insulation layer to form a dielectric antireflective coating thereon;        providing a reactive nitrogenous substance-free dielectric spacer layer on the antireflective coating silicon oxynitride layer to prevent reactive nitrogenous substance transport therethrough from the silicon oxynitride layer;        providing a photoresist layer on the dielectric spacer layer;        selectively exposing and developing the photoresist layer to uncover selective pattern portions of the underlying dielectric spacer layer, which pattern portions are in overlying relation to the first conductive layer region in the substrate;        removing the uncovered pattern portions of the dielectric spacer layer and corresponding underlying portions of the silicon oxynitride layer for uncovering corresponding portions of the underlying insulation layer; and        removing the uncovered portions of the insulation layer to uncover corresponding portions of the region of the first conductive layer in the substrate.        
U.S. Pat. No. 6,187,672 B1 disclose a method for forming interconnect structures and a semiconductor body, comprising:                (a) depositing a first metal layer on a semiconductor body;        (b) depositing a sacrificial layer on the first metal layer, the sacrificial layer having a height;        (c) patterning the sacrificial layer and the first metal layer to form separate metal lines with a sacrificial layer cap on the metal lines;        (d) depositing a low-k material to fill gaps between the metal lines and to cover the sacrificial layer;        (e) removing the low-k material to a level within the height of the sacrificial layer;        (f) removing the sacrificial layer;        (g) depositing a protective layer to cover the metal lines and the low-k material;        (h) depositing an insulator on the protective layer; depositing and patterning a photoresist layer on the insulator;        (i) creating vias in the insulator;        (j) performing a photoresist strip;        (k) performing a set clean; and        (l) selectively etching the protective layer using an anisotropic etch configured to leave a spacer on a vertical portion of the low-k material in the vias.        
A method of forming controlled voids in interlevel dielectrics is utilized in forming an integrated circuit in U.S. Pat. No. 5,960,311. The method comprises:                forming a insulation layer over a surface of a semiconducting surface of a body;        planarizing the insulation layer;        forming a metallization layer over the insulation layer;        patterning the metallization layer to form a plurality of metal signal lines;        forming a first conformal interlevel dielectric over the metallization layer and over the insulation layer so as to form sealed voids in the first conformal interlevel dielectric between at least some adjacent metal signal lines;        removing an upper portion of the first conformal interlevel dielectric to achieve a planar top surface, thereby exposing a first group of voids at the planar top surface and maintaining a second group of voids sealed at a depth below the planar top surface;        depositing a first flowable dielectric on the planar top surface of the first conformal interlevel dielectric filling the first group of voids; and        forming a second conformal interlevel dielectric over the first flowable dielectric.        There is a need when providing low k inter-layer dielectric materials in combination with photolithography to prevent or substantially lessen resist poisoning effects and to eliminate other integration-related issues, as well as simplify the process, while simultaneously achieving lower cost than when using conventional low-k inter-layer dielectric deposition methods.        